TPS70151PWPRG4

TPS70151PWPRG4 from Texas Instruments is a Integrated Circuit 500-mA, dual-channel low-dropout voltage regulator with power good & enable - Linear & low-dropout (LDO) regulators. TPS701xx family devices are designed to provide a complete power management solution for the TMS320 DSP family, processor power, ASIC, FPGA, and digital applications where dual output voltage regulators are required. Easy programmability of the sequencing function makes the TPS701xx family ideal for any TMS320 DSP applications with power sequencing requirements. Differentiated features, such as accuracy, fast transient response, SVS supervisory circuit, manual reset inputs, and an enable function, provide a complete system solution. The TPS701xx family of voltage regulators offer very low dropout voltage and dual outputs with power-up sequence control, which is designed primarily for DSP applications. These devices have extremely low noise output performance without using any added filter bypass capacitors and are designed to have a fast transient response and be stable with 10µF low ESR capacitors. These devices have fixed 3.3V/2.5V, 3.3V/1.8V, 3.3V/1.5V, 3.3V/1.2V, and adjustable/adjustable voltage options. Regulator 1 can support up to 500mA, and regulator 2 can support up to 250mA. Separate voltage inputs allow the designer to configure the source power. Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 170mV on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (maximum of 230µA over the full range of output current). This LDO family also features a sleep mode; applying a high signal to EN (enable) shuts down both regulators, reducing the input current to 1µA at T J = +25°C. The device is enabled when the EN pin is connected to a low-level input voltage. The output voltages of the two regulators are sensed at the V SENSE1 and V SENSE2 pins, respectively. The input signal at the SEQ pin controls the power-up sequence of the two regulators. When the device is enabled and the SEQ terminal is pulled high or left open, V OUT2 turns on first and V OUT1 remains off until V OUT2 reaches approximately 83% of its regulated output voltage. At that time V OUT1 is turned on. If V OUT2 is pulled below 83% (for example, an overload condition), V OUT1 is turned off. Pulling the SEQ terminal low reverses the power-up order and V OUT1 is turned on first. The SEQ pin is connected to an internal pull-up current source. For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator is turned off (disabled). The PG1 pin reports the voltage conditions at V OUT1, which can be used to implement an SVS for the circuitry supplied by regulator 1. The TPS701xx features a RESET (SVS, POR, or Power-On Reset). RESET output initiates a reset in DSP systems and related digital applications in the event of an undervoltage condition. RESET indicates the status of V OUT2 and both manual reset pins (MR1 and MR2). When V OUT2 reaches 95% of its regulated voltage and MR1 and MR2 are in the logic high state, RESET goes to a high impedance state after a 120ms delay. RESET goes to the logic low state when the V OUT2 regulated output voltage is pulled below 95% (for example, an overload condition) of its regulated voltage. To monitor V OUT1, the PG1 output pin can be connected to MR1 or MR2. The device has an undervoltage lockout (UVLO) circuit that prevents the internal regulators from turning on until V IN1 reaches 2.5V.

Base Number: TPS70151
Package: Tape & Reel
Standard Package: 2,000
RoHS: ROHS3 Compliant
REACH: Unaffected
MSL: 1 Year
ECCN: EAR99
HTSUS: 8542.39.0001

Integrated Circuits (ICs) / Power Management (PMIC) / Voltage Regulators - Linear