Search results for “jm38510”

JM38510/36001B2A from Texas Instruments is a 10-Line To 4-Line And 8-Line To 3-Line Priority Encoders - Digital multiplexers & encoders. These TTL encoders feature priority decoding of the inputs to ensure that only the highest-order data line is encoded. The '147 and 'LS147 encode nine data lines to four-line (8-4-2-1) BCD. The implied decimal zero condition requires no input condition as zero is encoded when all nine data lines are at a high logic level. The '148 and 'LS148 encode eight data lines to three-line (4-2-1) binary (octal). Cascading circuitry (enable input E1 and enable output E0) has been provided to allow octal expansion without the need for external circuitry. For all types, data inputs and outputs are active at the low logic level. All inputs are buffered to represent one normalized Series 54/74 or 54LS/74LS load, respectively.

JM38510/31004SDA from Texas Instruments is a JANS, 4-channel 2-input, 4.5V to 5.5V 16mA drive strength bipolar AND gate - AND gates. These devices contain four independent 2-input AND gates. The SN5408, SN54LS08, and SN54S08 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN7408, SN74LS08 and SN74S08 are characterized for operation from 0° to 70°C.

JM38510/34201BFA from Texas Instruments is a 4-Bit Binary Full Adders With Fast Carry - Specialty logic ICs. The ´F283 is a full adder that performs the addition of two 4-bit binary words. The sum () outputs are provided for each bit and the resultant carry (C4) output is obtained from the fourth bit. The device features full internal look-ahead across all four bits generating the carry term C4 in typically 5.7 ns. This capability provides the system designer with partial look-ahead performance at the economy and reduced package count of a ripple-carry implementation. The adder logic, including the carry, is implemented in its true form. End-around carry can be accomplished without the need for logic or level inversion. The ´F283 can be used with either all-active-high (positive logic) or all-active-low (negative logic) operands. The SN54F283 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F283 is characterized for operation from 0°C to 70°C.

JM38510/30001SCA from Texas Instruments is a JANS, 4-channel 2-input, 4.5V to 5.5V bipolar NAND gates - NAND gates. The SNx4xx00 devices contain four independent, 2-input NAND gates. The devices perform the Boolean function Y = A.B or Y = A + B in positive logic.

JM38510/17601BEA from Texas Instruments is a CMOS 8-Bit Addressable Latch - Other latches. CD4099B 8-bit addressable latch is a serial-input, parallel-output storage register that can perform a variety of functions. Data are inputted to a particular bit in the latch when that bit is addressed (by means of input A0, A1, A2) and when WRITE DISABLE is at a low level. When WRITE DISABLE is high, data entry is inhibited; however, all 8 outputs can be continuously read independent of WRITE DISABLE and address inputs. A master RESET input is available, which resets all bits to a logic "0" level when RESET and WRITE DISABLE are at a high level. When RESET is at a high level, and WRITE RESET is at a low level, the latch acts as a 1-of-8 demultiplexer; the bit that is addressed has an active output which follows the data input, while all unaddressed bits are held to a logic "0" level. The CD4099B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic package (E suffix), 16-lead small-outline package (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

JM38510/36001BEA from Texas Instruments is a 10-Line To 4-Line And 8-Line To 3-Line Priority Encoders - Digital multiplexers & encoders. These TTL encoders feature priority decoding of the inputs to ensure that only the highest-order data line is encoded. The '147 and 'LS147 encode nine data lines to four-line (8-4-2-1) BCD. The implied decimal zero condition requires no input condition as zero is encoded when all nine data lines are at a high logic level. The '148 and 'LS148 encode eight data lines to three-line (4-2-1) binary (octal). Cascading circuitry (enable input E1 and enable output E0) has been provided to allow octal expansion without the need for external circuitry. For all types, data inputs and outputs are active at the low logic level. All inputs are buffered to represent one normalized Series 54/74 or 54LS/74LS load, respectively.

The JM38510/65305BEA from Texas Instruments is a dual JK-type flip-flop Integrated Circuit with 2 elements and 1 bit per element, negative edge, in a 16-CDIP (0.300" 7.62mm) package.

JM38510/30608B2A from Texas Instruments is a Parallel-Load 8-Bit Shift Registers - Shift registers. The ’165 and ’LS165A are 8-bit serial shift registers that shift the data in the direction of Q A toward Q H when clocked. Parallel-in access to each stage is made available by eight individual, direct data inputs that are enabled by a low level at the shift/load (SH/LD) input. These registers also feature gated clock (CLK) inputs and complementary outputs from the eighth bit. All inputs are diode-clamped to minimize transmission-line effects, thereby simplifying system design. Clocking is accomplished through a two-input positive-NOR gate, permitting one input to be used as a clock-inhibit function. Holding either of the clock inputs high inhibits clocking, and holding either clock input low with SH/LD high enables the other clock input. Clock inhibit (CLK INH) should be changed to the high level only while CLK is high. Parallel loading is inhibited as long as SH/LD is high. Data at the parallel inputs are loaded directly into the register while SH/LD is low, independently of the levels of CLK, CLK INH, or serial (SER) inputs.

JM38510/30005SDA from Texas Instruments is a JANS, 3-channel 3-input, 4.5V to 5.5V bipolar NAND gates - NAND gates. These devices contain three independent 3-input NAND gates. The SN5410, SN54LS10, and SN54S10 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN7410, SN74LS10 and SN74S10 are characterized for operation from 0°C to 70°C.

The JM38510/32501SRA from Texas Instruments is a D-type flip-flop Integrated Circuit with clear, 8 B.

The JM38510/50403BRA from Texas Instruments is an OT PLD Integrated Circuit rated at 30 ns, using TTL logic in a CDIP20 package, with PLD Integrated Circuit macrocells.

The JM38510/50407BRA from Texas Instruments is a PAL programmable logic device Integrated Circuit in a 20-pin CDIP package, with PLD Integrated Circuit macrocells.

The JM38510/65352SCA from Texas Instruments is an HCT-series flip-flop with 2 functions and positive-edge triggering.

The JM38510/50401BRA from Texas Instruments is an OT PLD Integrated Circuit rated at 30 ns, using TTL logic in a CDIP20 package, with PLD Integrated Circuit macrocells.

The JM38510/38301BRA from Texas Instruments is a 54ALS240A octal buffers/drivers Integrated Circuit with element bit per element output.

The JM38510/65852BFA from Texas Instruments is a 3-line-to-8 decoder Integrated Circuit.

JM38510/30701SEA from Texas Instruments is a JANS, 3-Line To 8-Line Decoders/Demultiplexers - Digital demultiplexers & decoders. These Schottky-clamped TTL MSI circuits are designed to be used in high-performance memory decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the Schottky-clamped system decoder is negligible. The 'LS138, SN54S138, and SN74S138A decode one of eight lines dependent on the conditions at the three binary select inputs and the three enable inputs. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications. All of these decoder/demultiplexers feature fully buffered inputs, each of which represents only one normalized load to its driving circuit. All inputs are clamped with high-performance Schottky diodes to suppress line-ringing and to simplify system design. The SN54LS138 and SN54S138 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LS138 and SN74S138A are characterized for operation from 0°C to 70°C.

JM38510/33701BEA from Texas Instruments is a 3-Line To 8-Line Decoders/Demultiplexers - Digital demultiplexers & decoders. The ´F138 is designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible. The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications. The SN54F138 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F138 is characterized for operation from 0°C to 70°C.

JM38510/37701B2A from Texas Instruments is a 3-Line To 8-Line Decoders/Demultiplexers - Digital demultiplexers & decoders. The ´ALS138A and ´AS138 are 3-line to 8-line decoders/demultiplexers designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance systems, these devices can be used to minimize the effects of system decoding. When employed with high-speed memories with a fast enable circuit, the delay times of the decoder and the enable time of the memory are usually less than the typical access time of the memory. The effective system delay introduced by the Schottky-clamped system decoder is negligible. The conditions at the binary-select (A, B, and C) inputs and the three enable (G1,, and) inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications. The SN54ALS138A and SN54AS138 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS138A and SN74AS138 are characterized for operation from 0°C to 70°C.

The JM38510/65101SDA from Texas Instruments is an HC/UH series NOR gate Integrated Circuit providing 4 functions.

The JM38510/66302SEA from Texas Instruments is a binary counter Integrated Circuit (HC/UH SERIES, SY).

JM38510/65802BEA from Texas Instruments is a 3-Line To 8-Line Decoders/Demultiplexers - Digital demultiplexers & decoders. The SNx4HC138 devices are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories using a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.

The JM38510/30109SEA from Texas Instruments is a J-K flip-flop Integrated Circuit.

JM38510/65852BEA from Texas Instruments is a 3-Line To 8-Line Decoders/Demultiplexers - Digital demultiplexers & decoders

JM38510/65802B2A from Texas Instruments is a 3-Line To 8-Line Decoders/Demultiplexers - Digital demultiplexers & decoders. The SNx4HC138 devices are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories using a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.

JM38510/07701BFA from Texas Instruments is a 3-Line To 8-Line Decoders/Demultiplexers - Inverting buffers & drivers. These Schottky-clamped TTL MSI circuits are designed to be used in high-performance memory decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the Schottky-clamped system decoder is negligible. The 'LS138, SN54S138, and SN74S138A decode one of eight lines dependent on the conditions at the three binary select inputs and the three enable inputs. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications. All of these decoder/demultiplexers feature fully buffered inputs, each of which represents only one normalized load to its driving circuit. All inputs are clamped with high-performance Schottky diodes to suppress line-ringing and to simplify system design. The SN54LS138 and SN54S138 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LS138 and SN74S138A are characterized for operation from 0°C to 70°C.

The JM38510/30107SFA from Texas Instruments is an LS series TTL D flip-flop.

The JM38510/30109SFA from Texas Instruments is a J-K flip-flop logic Integrated Circuit.

The JM38510/05052BCA from Texas Instruments is a dual 4-input CMOS gate Integrated Circuit (CD4012B-MIL).

JM38510/38003BEA from Texas Instruments is a Synchronous 4-Bit Up/Down Binary Counters - Counters. These synchronous 4-bit up/down binary presettable counters feature an internal carry look-ahead circuitry for cascading in high-speed counting applications. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable (,) inputs and internal gating. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform. These counters are fully programmable; that is, they may be preset to either level. The load-input circuitry allows loading with the carry-enable output of cascaded counters. Because loading is synchronous, setting up a low level at the load (LOAD) input disables the counter and causes the outputs to agree with the data inputs after the next clock pulse. The internal carry look-ahead circuitry provides for cascading counters for n-bit synchronous application without additional gating. and inputs and a ripple-carry output () are instrumental in accomplishing this function. Both and must be low to count. The direction of the count is determined by the level of the up/down (U/D) input. When U/D is high, the counter counts up; when low, it counts down. is fed forward to enable., thus enabled, produces a low-level pulse while the count is zero (all inputs low) counting down or maximum (15) counting up. This low-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at or are allowed regardless of the level of the clock input. All inputs are diode clamped to minimize transmission-line effects, thereby simplifying system design. These counters feature a fully independent clock circuit. Changes at control inputs (,,, or U/D) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times. The SN54ALS169B and SN54AS169A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS169B and SN74AS169A are characterized for operation from 0°C to 70°C.

The JM38510/65203SCA from Texas Instruments is an AND gate Integrated Circuit from the HC/UH series with 4 functions.

JM38510/38002B2A from Texas Instruments is a Synchronous 4-Bit Binary Counters - Counters. These synchronous, presettable, 4-bit decade and binary counters feature an internal carry look-ahead circuitry for application in high-speed counting designs. The SN54ALS162B is a 4-bit decade counter. The x92ALS161B, x92ALS163B, x92AS161, and x92AS163 devices are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincidentally with each other when instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock input waveform. These counters are fully programmable; they can be preset to any number between 0 and 9 or 15. Because presetting is synchronous, setting up a low level at the load (LOAD) input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs. The clear function for the x92ALS161B and x92AS161 devices is asynchronous. A low level at the clear (CLR) input sets all four of the flip-flop outputs low, regardless of the levels of the CLK, LOAD, or enable inputs. The clear function for the SN54ALS162B, x92ALS163B, and x92AS163 devices is synchronous, and a low level at CLR sets all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The active-low output of the gate used for decoding is connected to CLR to synchronously clear the counter to 0000 (LLLL). The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. ENP and ENT inputs and a ripple-carry (RCO) output are instrumental in accomplishing this function. Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. RCO, thus enabled, produces a high-level pulse while the count is maximum (9 or 15, with Q A high). The high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK. These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times. The SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, and SN54AS163 are characterized for operation over the full military temperature range of x9655°C to 125°C. The SN74ALS161B, SN74ALS163B, SN74AS161, and SN74AS163 are characterized for operation from 0°C to 70°C.

The JM38510/50607BRA from Texas Instruments is an OT programmable logic device (PLD) Integrated Circuit with macrocells, rated 30 ns in TTL, in a CDIP20 package.

The JM38510/34601BSA from Texas Instruments is a 54F373 octal transparent latch Integrated Circuit with element bit per element output.

The JM38510/30904BFA from Texas Instruments is a bipolar 1-element, 8-input multiplexer.

The JM38510/33202BRA from Texas Instruments is an octal buffer and driver Integrated Circuit, 54F241, with specifications for element, bit per element and output.

JM38510/30701B2A from Texas Instruments is a 3-Line To 8-Line Decoders/Demultiplexers - Digital demultiplexers & decoders. These Schottky-clamped TTL MSI circuits are designed to be used in high-performance memory decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the Schottky-clamped system decoder is negligible. The 'LS138, SN54S138, and SN74S138A decode one of eight lines dependent on the conditions at the three binary select inputs and the three enable inputs. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications. All of these decoder/demultiplexers feature fully buffered inputs, each of which represents only one normalized load to its driving circuit. All inputs are clamped with high-performance Schottky diodes to suppress line-ringing and to simplify system design. The SN54LS138 and SN54S138 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LS138 and SN74S138A are characterized for operation from 0°C to 70°C.

The JM38510/65602SRA from Texas Instruments is a D-type flip-flop Integrated Circuit with element and bit specifications; its source description reads "with 3" and is incomplete.

The JM38510/37203B2A from Texas Instruments is a 54ALS373A octal D-type transparent latch Integrated Circuit with element bit per element output.

The JM38510/36101SEA from Texas Instruments is a TTL D flip-flop in the LS series.

The JM38510/08201BEA from Texas Instruments is a 4-bit magnitude comparator logic Integrated Circuit of the SN54S85 type.

The JM38510/53001BQA from Intel is an 8086 16-bit microprocessor Integrated Circuit.

JM38510/11804SYA from Texas Instruments is a -4.2V to -40V, 1.5A adjustable output negative linear regulator - Linear & low-dropout (LDO) regulators. The LM137 are adjustable 3-terminal negative voltage regulators capable of supplying in excess of -1.5A over an output voltage range of -37V to -1.2V. These regulators are exceptionally easy to apply, requiring only 2 external resistors to set the output voltage and 1 output capacitor for frequency compensation. The circuit design has been optimized for excellent regulation and low thermal transients. Further, the LM137 series features internal current limiting, thermal shutdown and safe-area compensation, making them virtually blowout-proof against overloads. The LM137 serves a wide variety of applications including local on-card regulation, programmable-output voltage regulation or precision current regulation. The LM137 are ideal complements to the LM117 adjustable positive regulators.

JM38510/38001B2A from Texas Instruments is a Synchronous 4-Bit Binary Counters - Counters. These synchronous, presettable, 4-bit decade and binary counters feature an internal carry look-ahead circuitry for application in high-speed counting designs. The SN54ALS162B is a 4-bit decade counter. The x92ALS161B, x92ALS163B, x92AS161, and x92AS163 devices are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincidentally with each other when instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock input waveform. These counters are fully programmable; they can be preset to any number between 0 and 9 or 15. Because presetting is synchronous, setting up a low level at the load (LOAD) input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs. The clear function for the x92ALS161B and x92AS161 devices is asynchronous. A low level at the clear (CLR) input sets all four of the flip-flop outputs low, regardless of the levels of the CLK, LOAD, or enable inputs. The clear function for the SN54ALS162B, x92ALS163B, and x92AS163 devices is synchronous, and a low level at CLR sets all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The active-low output of the gate used for decoding is connected to CLR to synchronously clear the counter to 0000 (LLLL). The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. ENP and ENT inputs and a ripple-carry (RCO) output are instrumental in accomplishing this function. Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. RCO, thus enabled, produces a high-level pulse while the count is maximum (9 or 15, with Q A high). The high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK. These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times. The SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, and SN54AS163 are characterized for operation over the full military temperature range of x9655°C to 125°C. The SN74ALS161B, SN74ALS163B, SN74AS161, and SN74AS163 are characterized for operation from 0°C to 70°C.

JM38510/32502SRA from Texas Instruments is a JANS, Octal D-Type Transparent Latches with 3-state Outputs - D-type latches. These 8-bit registers feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The high-impedance 3-state and increased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pullup components. These devices are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches of the ’LS373 and ’S373 are transparent D-type latches, meaning that while the enable (C or CLK) input is high, the Q outputs follow the data (D) inputs. When C or CLK is taken low, the output is latched at the level of the data that was set up. The eight flip-flops of the ’LS374 and ’S374 are edge-triggered D-type flip-flops. On the positive transition of the clock, the Q outputs are set to the logic states that were set up at the D inputs. Schmitt-trigger buffered inputs at the enable/clock lines of the ’S373 and ’S374 devices simplify system design as ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A buffered output-control (OC) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. OC does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new data can be entered, even while the outputs are off.

The JM38510/17504BEA from Texas Instruments is a CD4098B-MIL CMOS dual monostable multivibrator.