Search results for “74LVTH573”

74LVTH573MSA from Fairchild Semiconductor is a BUS DRIVER, LVT SERIES

74LVTH573WMX from Fairchild Semiconductor is a BUS DRIVER, LVT SERIES

74LVTH573WMX from onsemi is a IC LATCH TRANSP OCT 3ST 20SOIC

The 74LVTH573WM from onsemi is a D-type transparent latch Integrated Circuit with 1 channel, 8:8 configuration and tri-state outputs, in a 20-SOIC package.

74LVTH573WM from Fairchild Semiconductor is a BUS DRIVER, LVT SERIES

74LVTH573SJX from onsemi is a IC LATCH TRANSP OCT 3ST 20SOP

The 74LVTH573SJ from onsemi is a transparent octal latch with 3-state outputs in a 20-SOP package.

The SN74LVTH573RGYR from Texas Instruments is a single D-type transparent latch Integrated Circuit with an 8:8 configuration, in a 20-VQFN package.

SN74LVTH573PW from Texas Instruments is a Integrated Circuit 3.3-V ABT Octal Transparent D-Type Latches With 3-State Outputs - D-type latches. These octal latches are designed specifically for low-voltage (3.3-V) V CC operation, but with the capability to provide a TTL interface to a 5-V system environment. The eight latches of the ’LVTH573 devices are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. These devices are fully specified for hot-insertion applications using I off and power-up 3-state. The I off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

The SN74LVTH573GQNR from Texas Instruments is a D-type transparent latch Integrated Circuit with 1 channel, 8:8 tri-state outputs, in a 20-BGA MicroStar Junior (4x3) package.

The SN74LVTH573ZQNR from Texas Instruments is a D-type transparent latch with 1 channel and an 8:8 configuration, with a tri-state output, in a 20-BGA MicroStar Junior (4x3) package.

SN74LVTH573DB from Texas Instruments is a IC OCTAL LATCH TRI-STATE 20-SSOP

SN74LVTH573PWR from Texas Instruments is a Integrated Circuit 3.3-V ABT Octal Transparent D-Type Latches With 3-State Outputs - D-type latches. These octal latches are designed specifically for low-voltage (3.3-V) V CC operation, but with the capability to provide a TTL interface to a 5-V system environment. The eight latches of the ’LVTH573 devices are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. These devices are fully specified for hot-insertion applications using I off and power-up 3-state. The I off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

SN74LVTH573DBR from Texas Instruments is a Integrated Circuit 3.3-V ABT Octal Transparent D-Type Latches With 3-State Outputs - D-type latches. These octal latches are designed specifically for low-voltage (3.3-V) V CC operation, but with the capability to provide a TTL interface to a 5-V system environment. The eight latches of the ’LVTH573 devices are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. These devices are fully specified for hot-insertion applications using I off and power-up 3-state. The I off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

The SN74LVTH573NSR from Texas Instruments is a D-type transparent latch with 1 channel, an 8:8 configuration and tri-state outputs, in a 20-SO package.

The SN74LVTH573DWR from Texas Instruments is a D-type transparent latch with 1 channel, 8:8 configuration and tri-state output, in a 20-SOIC package.

SN74LVTH573IPWREP from Texas Instruments is a Integrated Circuit Enhanced Product 3.3-V Abt Octal Transparent D-Type Latches With 3-State Outputs - D-type latches. This octal latch is designed specifically for low-voltage (3.3-V) V CC operation, but with the capability to provide a TTL interface to a 5-V system environment. The eight latches of the SN74LVTH573 are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. This device is fully specified for hot-insertion applications using I off and power-up 3-state. The I off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

The SN74LVTH573DWRE4 from Texas Instruments is an ABT octal transparent D-type latch Integrated Circuit in a 20-SOIC package.

The SN74LVTH573DW from Texas Instruments is a 3.3 V D-type transparent latch Integrated Circuit with 1 channel, an 8:8 configuration and tri-state outputs, in a 20-SOIC package.