Search results for “74lvth574”

The 74LVTH574D,118 from NXP USA Inc. is a single D-type flip-flop Integrated Circuit with 1 element, 8-bit width and positive edge triggering, in a 20-SOIC package (0.295", 7.50 mm width).

74LVTH574SJX from onsemi is a IC FF D-TYPE SNGL 8BIT 20SOP

74LVTH574MTCX from Fairchild Semiconductor is a IC FF D-TYPE SNGL 8BIT 20TSSOP

74LVTH574D,112 from NXP USA Inc. is a IC FF D-TYPE SNGL 8BIT 20SO

74LVTH574WM from onsemi is a IC FF D-TYPE SNGL 8BIT 20SOIC

74LVTH574WM from Fairchild Semiconductor is a IC FF D-TYPE SNGL 8BIT 20SOIC

74LVTH574MTC from Fairchild Semiconductor is a IC FF D-TYPE SNGL 8BIT 20TSSOP

The 74LVTH574SJ from onsemi is a 1-element D-type flip flop with 8 bits and positive edge triggering, in a 20-SOIC (0.209", 5.30 mm width) package.

74LVTH574MSA from Fairchild Semiconductor is a IC FF D-TYPE SNGL 8BIT 20SSOP

74LVTH574WMX from onsemi is a IC FF D-TYPE SNGL 8BIT 20SOIC

74LVTH574WMX from Fairchild Semiconductor is a IC FF D-TYPE SNGL 8BIT 20SOIC

SN74LVTH574ZQNR from Texas Instruments is a IC FF D-TYPE SNGL 8BIT 20BGA

SN74LVTH574DWR from Texas Instruments is a IC FF D-TYPE SNGL 8BIT 20SOIC

SN74LVTH574PWR from Texas Instruments is a Integrated Circuit 3.3-V ABT Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs - D-type flip-flops. These octal flip-flops are designed specifically for low-voltage (3.3-V) V CC operation, but with the capability to provide a TTL interface to a 5-V system environment. The eight flip-flops of the ’LVTH574 devices are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. These devices are fully specified for hot-insertion applications using I off and power-up 3-state. The I off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

SN74LVTH574PW from Texas Instruments is a Integrated Circuit 3.3-V ABT Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs - D-type flip-flops. These octal flip-flops are designed specifically for low-voltage (3.3-V) V CC operation, but with the capability to provide a TTL interface to a 5-V system environment. The eight flip-flops of the ’LVTH574 devices are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. These devices are fully specified for hot-insertion applications using I off and power-up 3-state. The I off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

The SN74LVTH574DW from Texas Instruments is an 8-bit D-type flip-flop with 1 element and positive edge, in a 20-SOIC (0.295", 7.50 mm width) package.

SN74LVTH574IPWREP from Texas Instruments is a Integrated Circuit Enhanced Product 3.3-V Abt Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs - D-type flip-flops. This octal flip-flop is designed specifically for low-voltage (3.3-V) V CC operation, but with the capability to provide a TTL interface to a 5-V system environment. The eight flip-flops of the SN74LVTH574 are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. This device is fully specified for hot-insertion applications using I off and power-up 3-state. The I off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

SN74LVTH574DBR from Texas Instruments is a Integrated Circuit 3.3-V ABT Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs - D-type flip-flops. These octal flip-flops are designed specifically for low-voltage (3.3-V) V CC operation, but with the capability to provide a TTL interface to a 5-V system environment. The eight flip-flops of the ’LVTH574 devices are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. These devices are fully specified for hot-insertion applications using I off and power-up 3-state. The I off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

The SN74LVTH574GQNR from Texas Instruments is a D-type flip-flop Integrated Circuit with 1 element of 8 bits per element, positive edge triggered, in a 20-VFBGA package.

SN74LVTH574RGYR from Texas Instruments is a IC FF D-TYPE SNGL 8BIT 20VQFN

SN74LVTH574DB from Texas Instruments is a Integrated Circuit 3.3-V ABT Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs - D-type flip-flops. These octal flip-flops are designed specifically for low-voltage (3.3-V) V CC operation, but with the capability to provide a TTL interface to a 5-V system environment. The eight flip-flops of the ’LVTH574 devices are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. These devices are fully specified for hot-insertion applications using I off and power-up 3-state. The I off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

The SN74LVTH574NSR from Texas Instruments is a single 8-bit D-type flip-flop Integrated Circuit in a 20-SO package.

DM74LS377N from onsemi is a IC FF D-TYPE SNGL 8BIT 20DIP