Search results for “BU-27”

BU-27 from Mueller Electric Co is a HD CLIP STEEL NON-INSULATED 20A

BU-27M from Mueller Electric Co is a HD CLIP COPPER NON-INSULATED 40A

BU-27X from Mueller Electric Co is a HD CLIP SS NON-INSUL 20A

BU-27CG from Mueller Electric Co is a GEOPHONE CLP COPPR NON-INSUL 40A

BU-27CGW from Mueller Electric Co is a GEOPHONE CLP COPPR NON-INSUL 40A

BU-27C from Mueller Electric Co is a HD CLIP COPPER NON-INSULATED 40A

BU-29-9 from Mueller Electric Co is a INSULATOR FOR BU-27 SERIES WHITE

BU-29-0 from Mueller Electric Co is a INSULATOR FOR BU-27 SERIES BLACK

BU-29-4 from Mueller Electric Co is a INSULATOR FOR BU-27 SERIES YELLW

BU-29-2 from Mueller Electric Co is a INSULATOR FOR BU-27 SERIES RED

BU-29-5 from Mueller Electric Co is a INSULATOR FOR BU-27 SERIES GREEN

SN75971B2DL from Texas Instruments is a Integrated Circuit SCSI differential converter-data - Other interfaces. The SN75971B SCSI differential converter-data is a 9-channel RS-485 transceiver. When used in conjunction with its companion control transceiver, the SN75970B, the resulting chip set provides the superior electrical performance of differential SCSI from a single-ended SCSI bus or controller. A 16-bit Ultra-SCSI (or Fast-20) SCSI bus can be implemented with just three devices (two data and one control) in the space efficient, 56-pin, shrink small-outline package (SSOP) or thin shink small outline package (TSSOP) and a few external components. An 8-bit SCSI bus requires only one data and one control transceiver. The SN75971B is available in a B2 (20 Mxfer) version and a B1 (10 Mxfer) version. In a typical differential SCSI node, the SCSI controller provides an enable for each external RS-485 transceiver channel. This could require as many as 27 extra terminals for a 16-bit differential bus controller or relegate a 16-bit, single-ended controller to only an 8-bit differential bus. Using the standard nine SCSIcontrol signals, the SN75970B control transceiver decodes the state of the bus and enables the SN75971B data transceiver to transmit the single-ended SCSI input signals (A side) differentially to the cable or receive the differential cable signals (B side) and drive the single-ended outputs to the controller. A reset function, which disables all outputs and clears internal latches, can be accomplished from two external inputs and two internally-generated signals. RESET (reset) and DSENS (differential sense) are available to external circuits for a bus reset or to disable all outputs should a single-ended cable be inadvertently connected to a differential connector. Internally-generated power-up and thermal-shutdown signals have the same affect when the supply voltage is below approximately 3.5 V or the junction temperature exceeds 175°C. The SCSI, differential, converter-data chip operates in two modes depending on the state of the DRVBUS input. With DRVBUS low, a bidirectional latch circuit sets the direction of data transfer. Each data bit has its own latch, and each bit's direction is independent of all other bits. When neither the single-ended nor the differential sides are asserted, the latch disables both A- and B-side output drivers. When the input to either side is asserted, the latch enables the opposite side's driver and sets data flow from the asserted input to the opposite side of the device. When the input deasserts, the latch maintains the direction until the receiver on the enabled driver detects a deassertion. The latch then returns to the initial state. No parity checking is done by this device; the parity signal passes through the device like other data signals do. When DRVBUS is high, direction is determined by the SDB signal. However, a change in SDB does not always immediately change the direction. When DRVBUS first asserts, the direction indicated by SDB is latched and takes effect immediately. When SDB changes while DRVBUS is high, the drivers that were on immediately turn off. However, the other driver set does not turn on until the receivers sense a deasserted state on all nine data lines. This is done to prevent the active drivers from turning on until all other drivers are off and the terminators pull the lines to a deasserted state. The single-ended SCSI bus interface consists of CMOS, bidirectional inputs and outputs. The drivers are rated to ±16 mA of output current. The receiver inputs are pulled high with approximately 4 mA to eliminate the need for external pullup resistors for the open-drain outputs of most single-ended SCSI controllers. The single-ended side of the device is not intended to drive the SCSI bus directly. The differential SCSI bus interface consists of bipolar, bidirectional inputs and outputs that meet or exceed the requirements of EIA-485 and ISO 8482-1982/TIA TR30.2 referenced by American National Standard of Information Systems (ANSI) X3.131-1994 Small Computer System Interface-2 (SCSI-2) and SCSI-3 Fast-20 Parallel Interface (Fast-20) X3.277:1996. The SN75971B is characterized for operation over the temperature range of 0°C to 70°C.

SNJ54LS670W from Texas Instruments is a 4-By-4 Register Files With 3-State Outputs - Specialty logic ICs. The SN54LS670 and SN74LS670 MSI 16-bit TTL register files incorporate the equivalent of 98 gates. The register file is organized as 4 words of 4 bits each and separate on-chip decoding is provided for addressing the four word locations to either write-in or retrieve data. This permits simultaneous writing into one location and reading from another word location. Four data inputs are available which are used to supply the 4-bit word to be stored. Location of the word is determined by the write-address inputs A and B in conjunction with a write-enable signal. Data applied at the inputs should be in its true form. That is, if a high-level signal is desired from the output, a high-level is applied at the data input for that particular bit location. The latch inputs are arranged so that new data will be accepted only if both internal address gate inputs are high. When this condition exists, data at the D input is transferred to the latch output. When the write-enable input, G W, is high, the data inputs are inhibited and their levels can cause no change in the information stored in the internal latches. When the read-enable input, G R, is high, the data outputs are inhibited and go into the high-impedance state. The individual address lines permit direct acquisition of data stored in any four of the latches. Four individual decoding gates are used to complete the address for reading a word. When the read address is made in conjunction with the read-enable signal, the word appears at the four outputs. This arrangement - data-entry addressing separate from data-read addressing and individual sense line - eliminates recovery times, permits simultaneous reading and writing, and is limited in speed only by the write time (27 nanoseconds typical) and the read time (24 nanoseconds typical). The register file has a nondestructive readout in that data is not lost when addressed. All inputs except read enable and write enable are buffered to lower the drive requirements to one Series 54LS/74LS standard load, and input-clamping diodes minimize switching transients to simplify system design. High-speed, double-ended AND-OR-INVERT gates are employed for the read-address function and have high-sink-current, three-state outputs. Up to 128 of these outputs may be bus connected for increasing the capacity up to 512 words. Any number of these registers may be paralleled to provide n-bit word length. The SN54LS670 is characterized for operation over the full military temperature range of -55°C to 125°C; the SN74LS670 is characterized for operation from 0°C to 70°C.

SN54LS670J from Texas Instruments is a 4-By-4 Register Files With 3-State Outputs - Specialty logic ICs. The SN54LS670 and SN74LS670 MSI 16-bit TTL register files incorporate the equivalent of 98 gates. The register file is organized as 4 words of 4 bits each and separate on-chip decoding is provided for addressing the four word locations to either write-in or retrieve data. This permits simultaneous writing into one location and reading from another word location. Four data inputs are available which are used to supply the 4-bit word to be stored. Location of the word is determined by the write-address inputs A and B in conjunction with a write-enable signal. Data applied at the inputs should be in its true form. That is, if a high-level signal is desired from the output, a high-level is applied at the data input for that particular bit location. The latch inputs are arranged so that new data will be accepted only if both internal address gate inputs are high. When this condition exists, data at the D input is transferred to the latch output. When the write-enable input, G W, is high, the data inputs are inhibited and their levels can cause no change in the information stored in the internal latches. When the read-enable input, G R, is high, the data outputs are inhibited and go into the high-impedance state. The individual address lines permit direct acquisition of data stored in any four of the latches. Four individual decoding gates are used to complete the address for reading a word. When the read address is made in conjunction with the read-enable signal, the word appears at the four outputs. This arrangement - data-entry addressing separate from data-read addressing and individual sense line - eliminates recovery times, permits simultaneous reading and writing, and is limited in speed only by the write time (27 nanoseconds typical) and the read time (24 nanoseconds typical). The register file has a nondestructive readout in that data is not lost when addressed. All inputs except read enable and write enable are buffered to lower the drive requirements to one Series 54LS/74LS standard load, and input-clamping diodes minimize switching transients to simplify system design. High-speed, double-ended AND-OR-INVERT gates are employed for the read-address function and have high-sink-current, three-state outputs. Up to 128 of these outputs may be bus connected for increasing the capacity up to 512 words. Any number of these registers may be paralleled to provide n-bit word length. The SN54LS670 is characterized for operation over the full military temperature range of -55°C to 125°C; the SN74LS670 is characterized for operation from 0°C to 70°C.