Universal Bus Functions

SN74ABT16501DLR from Texas Instruments is a Integrated Circuit 18-bit universal bus transceivers with 3-state outputs - General-purpose transceivers. These 18-bit universal bus transceivers consist of storage elements that can operate either as D-type latches or D-type flip-flops to allow data flow in transparent or clocked modes. Data flow in each direction is controlled by output-enable (OEAB and), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is high, the outputs are active. When OEAB is low, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B but uses, LEBA, and CLKBA. The output enables are complementary (OEAB is active high and is active low). To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor and should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sourcing/current-sinking capability of the driver. The SN54ABT16501 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT16501 is characterized for operation from -40°C to 85°C.

SN74GTL16612DL from Texas Instruments is a Integrated Circuit 18-Bit LVTTL-to-GTL/GTL+ Universal Bus Transceivers - Voltage translators. The 'GTL16612 devices are 18-bit UBT™ transceivers that provide LVTTL-to-GTL/GTL+ and GTL/GTL+-to-LVTTL signal-level translation. They combine D-type flip-flops and D-type latches to allow for transparent, latched, clocked, and clock-enabled modes of data transfer identical to the '16601 function. The devices provide an interface between cards operating at LVTTL logic levels and a backplane operating at GTL/GTL+ signal levels. Higher-speed operation is a direct result of the reduced output swing (<1 V), reduced input threshold levels, and OEC™ circuitry. The user has the flexibility of using these devices at either GTL (V TT = 1.2 V and V REF = 0.8 V) or the preferred higher noise margin GTL+ (V TT = 1.5 V and V REF = 1 V) signal levels. GTL+ is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The B port normally operates at GTL or GTL+ signal levels, while the A-port and control inputs are compatible with LVTTL logic levels and are 5-V tolerant. V REF is the reference input voltage for the B port. V CC (5 V) supplies the internal and GTL circuitry while V CC (3.3 V) supplies the LVTTL output buffers. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable(LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CEAB and CEBA) inputs. For A-to-B data flow, the devices operate in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CEAB is low and CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB if CEAB also is low. When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that for A to B, but uses OEBA, LEBA, CLKBA, and CEBA. These devices are fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. Active bus-hold circuitry holds unused or undriven LVTTL inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

The SN74AVC16334DGGR from Texas Instruments is a 16-bit universal bus driver Integrated Circuit in a 48-TSSOP package.

SN74ALVCH16269DGGR from Texas Instruments is a Integrated Circuit 12-bit to 24-bit registered bus exchanger with 3-state outputs - General-purpose transceivers. This 12-bit to 24-bit registered bus exchanger is designed for 1.65-V to 3.6-V V CC operation. The SN74ALVCH16269 is used in applications in which two separate ports must be multiplexed onto, or demultiplexed from, a single port. The device is particularly suitable as an interface between synchronous DRAMs and high-speed microprocessors. Data is stored in the internal B-port registers on the low-to-high transition of the clock (CLK) input when the appropriate clock-enable (CLKENA) inputs are low. Proper control of these inputs allows two sequential 12-bit words to be presented as a 24-bit word on the B port. For data transfer in the B-to-A direction, a single storage register is provided. The select (SEL) line selects 1B or 2B data for the A outputs. The register on the A output permits the fastest possible data transfer, extending the period during which the data is valid on the bus. The control terminals are registered so that all transactions are synchronous with CLK. Data flow is controlled by the active-low output enables (OEA, OEB1, OEB2). To ensure the high-impedance state during power up or power down, a clock pulse should be applied as soon as possible, and OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Due to OE being routed through a register, the active state of the outputs cannot be determined before the arrival of the first clock pulse. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

The SN74ALVCH16903DGVR from Texas Instruments is a 12-bit universal bus driver Integrated Circuit in a 56-TVSOP package.

SN74ABT162601DLR from Texas Instruments is a Integrated Circuit 18-bit universal bus transceivers with 3-state outputs - General-purpose transceivers. These 18-bit universal bus transceivers combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB and CLKENBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. Output-enable OEAB is active-low. When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, CLKBA, and CLKENBA. The B-port outputs, which are designed to source or sink up to 12 mA, include equivalent 25- series resistors to reduce overshoot and undershoot. When V CC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT162601 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT162601 is characterized for operation from -40°C to 85°C.

The 74ALVCF162835TX from Fairchild Semiconductor is an 18-bit universal bus driver in a 56-TSSOP package.

The SCAN16602SM/NOPB from Texas Instruments is a 16-bit universal bus transceiver in a 64-NFBGA (8x8) package.

The SN74ALVC16835GQLR from Texas Instruments is an 18-bit universal bus driver in a 56-BGA Microstar Junior (7 x 4.5) package.

SN74AVC16834DGGR from Texas Instruments is a Integrated Circuit 18-Bit Universal Bus Driver With 3-State Outputs - General-purpose transceivers. A Dynamic Output Control (DOC™) circuit is implemented, which, during the transition, initially lowers the output impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows typical V OL vs I OL and V OH vs I OH curves to illustrate the output impedance and drive capability of the circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC™) Circuitry Technology and Applications, literature number SCEA009. This 18-bit universal bus driver is operational at 1.2-V to 3.6-V V CC, but is designed specifically for 1.65-V to 3.6-V V CC operation. Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode when the latch-enable (LE) input is low. The A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is high, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE is high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

SN74ALVC16835DGGR from Texas Instruments is a Integrated Circuit 18-Bit Universal Bus Driver With 3-State Outputs - General-purpose transceivers. This 18-bit universal bus driver is designed for 1.65-V to 3.6-V V CC operation. Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode when the latch-enable (LE) input is high. The A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE is high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

SN74ABT16601DLR from Texas Instruments is a Integrated Circuit 18-bit universal bus transceivers with 3-state outputs - General-purpose transceivers. These 18-bit universal bus transceivers combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, clocked, and clock-enabled modes. Data flow in each direction is controlled by output-enable (and), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (and) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. Output enable is active low. When is low, the outputs are active. When is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B, but uses, LEBA, CLKBA, and. To ensure the high-impedance state during power up or power down, should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT16601 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT16601 is characterized for operation from -40°C to 85°C.

The SN74ALVCH16901DGGR from Texas Instruments is an 18-bit universal bus transceiver in a 64-TSSOP package.

The SN74GTLPH1655DGGR from Texas Instruments is a universal bus transceiver Integrated Circuit with 16-bit width, in a 64-TSSOP package.

The SN74ABTH18502APMR from Texas Instruments is an 18-bit scan test universal bus transceiver in a 64-LQFP (10x10) package.

The SN74ALVCH16903DLR from Texas Instruments is a 12-bit universal bus driver Integrated Circuit in a 56-SSOP package.

The SN74ABTH18504APM from Texas Instruments is a scan test universal bus transceiver with 20-bit width, in a 64-LQFP (10x10) package.

SN74ALVCH16501DGGR from Texas Instruments is a Integrated Circuit 18-bit universal bus transceiver with 3-state outputs - General-purpose transceivers. This 18-bit universal bus transceiver is designed for 1.65-V to 3.6-V V CC operation. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is high, the outputs are active. When OEAB is low, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, and CLKBA. The output enables are complementary (OEAB is active high and OEBA is active low). To ensure the high-impedance state during power up or power down, OEBA should be tied to V CC through a pullup resistor and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

SN74ALVC162334DLR from Texas Instruments is a Integrated Circuit 16-Bit Universal Bus Driver With 3-State Outputs - General-purpose transceivers. This 16-bit universal bus driver is designed for 1.65-V to 3.6-V V CC operation. Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode when the latch-enable (LE) input is low. When LE is high, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is high, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE is high, the outputs are in the high-impedance state. The outputs, which are designed to sink up to 12 mA, include equivalent 26- resistors to reduce overshoot and undershoot. To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

SN74ALVCH16903DL from Texas Instruments is a Integrated Circuit 3.3-V 12-Bit Universal Bus Driver with Parity Checker and Dual 3-State Outputs - General-purpose transceivers. This 12-bit universal bus driver is designed for 2.3-V to 3.6-V V CC operation. The SN74ALVCH16903 has dual outputs and can operate as a buffer or an edge-triggered register. In both modes, parity is checked on APAR, which arrives one cycle after the data to which it applies. The YERR output, which is produced one cycle after APAR, is open drain. MODE selects one of the two data paths. When MODE is low, the device operates as an edge-triggered register. On the positive transition of the clock (CLK) input and when the clock-enable (CLKEN) input is low, data set up at the A inputs is stored in the internal registers. On the positive transition of CLK and when CLKEN is high, only data set up at the 9A-12A inputs is stored in their internal registers. When MODE is high, the device operates as a buffer and data at the A inputs passes directly to the outputs. 11A/YERREN serves a dual purpose; it acts as a normal data bit and also enables YERR data to be clocked into the YERR output register. When used as a single device, parity output enable (PAROE) must be tied high; when parity input/output (PARI/O) is low, even parity is selected and when PARI/O is high, odd parity is selected. When used in pairs and PAROE is low, the parity sum is output on PARI/O for cascading to the second SN74ALVCH16903. When used in pairs and PAROE is high, PARI/O accepts a partial parity sum from the first SN74ALVCH16903. A buffered output-enable (OE) input can be used to place the 24 outputs and YERR in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect the internal operation of the device. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN74ALVCH16903 is characterized for operation from 0°C to 70°C.

The SN74ALVCH162525DL from Texas Instruments is a CMOS universal bus transceiver with 18 bits, in a 56-SSOP package.

SN74ALVC162836DGGR from Texas Instruments is a Integrated Circuit 20-Bit Universal Bus Driver With 3-State Outputs - General-purpose transceivers. This 20-bit universal bus driver is designed for 1.65-V to 3.6-V V CC operation. Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode when the latch-enable (LE) input is low. When LE is high, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is high, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE is high, the outputs are in the high-impedance state. The output port includes equivalent 26- series resistors to reduce overshoot and undershoot. To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74AVC16334DGVR from Texas Instruments is a 16-bit universal bus driver Integrated Circuit in a 48-TVSOP package.

SN74ALVCH16524DL from Texas Instruments is a Integrated Circuit 18-Bit Registered Bus Transceiver With 3-State Outputs - General-purpose transceivers. This 18-bit universal bus transceiver is designed for 1.65-V to 3.6-V V CC operation. Data flow in each direction is controlled by output-enable (OEAB and OEBA) and clock-enable (CLKENBA) inputs. For the A-to-B data flow, the data flows through a single buffer. The B-to-A data can flow through a four-stage pipeline register path, or through a single register path, depending on the state of the select (SEL) input. Data is stored in the internal registers on the low-to-high transition of the clock (CLK) input, provided that the appropriate CLKENBA input is low. The B-to-A data transfer is synchronized with CLK. To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.