Universal Bus Functions

SN74GTL16616DLR from Texas Instruments is a Integrated Circuit 17-bit LVTTL-to-GTL/GTL+ universal bus transceivers with buffered clock outputs - Voltage translators. The SN74GTL16616 is a 17-bit UBT™ transceiver that provides LVTTL-to-GTL/GTL+ and GTL/GTL+-to-LVTTL signal-level translation. Combined D-type flip-flops and D-type latches allow for transparent, latched, clocked, and clocked-enabled modes of data transfer identical to the '16601 function. Additionally, this device provides for a copy of CLKAB at GTL/GTL+ signal levels (CLKOUT) and conversion of a GTL/GTL+ clock to LVTTL logic levels (CLKIN). This device provides an interface between cards operating at LVTTL logic levels and a backplane operating at GTL/GTL+ signal levels. Higher-speed operation is a direct result of the reduced output swing (<1 V), reduced input threshold levels, and OEC™ circuitry. The user has the flexibility of using this device at either GTL (V TT = 1.2 V and V REF = 0.8 V) or the preferred higher noise margin GTL+ (V TT = 1.5 V and V REF = 1 V) signal levels. GTL+ is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The B port normally operates at GTL or GTL+ signal levels, while the A-port and control inputs are compatible with LVTTL logic levels and are 5-V tolerant. V REF is the reference input voltage for the B port. V CC (5 V) supplies the internal and GTL circuitry while V CC (3.3 V) supplies the LVTTL output buffers. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CEAB and CEBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CEAB is low and CLKAB is held at a high or low logic level. If LEAB is low, the A-bus data is stored in the latch/flip-flop on the low-to-high transition of CLKAB if CEAB also is low. When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, CLKBA, and CEBA. This device is fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. Active bus-hold circuitry holds unused or undriven LVTTL inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

SN74ALVCH162268GR from Texas Instruments is a Integrated Circuit 12-bit to 24-bit registered bus exchanger with 3-state outputs - General-purpose transceivers. This 12-bit to 24-bit registered bus exchanger is designed for 1.65-V to 3.6-V V CC operation. The SN74ALVCH162268 is used for applications in which data must be transferred from a narrow high-speed bus to a wide, lower-frequency bus. The device provides synchronous data exchange between the two ports. Data is stored in the internal registers on the low-to-high transition of the clock (CLK) input when the appropriate clock-enable (CLKEN) inputs are low. The select (SEL) line is synchronous with CLK and selects 1B or 2B input data for the A outputs. For data transfer in the A-to-B direction, a two-stage pipeline is provided in the A-to-1B path, with a single storage register in the A-to-2B path. Proper control of these inputs allows two sequential 12-bit words to be presented synchronously as a 24-bit word on the B port. Data flow is controlled by the active-low output enables (OEA, OEB). These control terminals are registered, so bus direction changes are synchronous with CLK. The B outputs, which are designed to sink up to 12 mA, include equivalent 26- resistors to reduce overshoot and undershoot. To ensure the high-impedance state during power up or power down, a clock pulse should be applied as soon as possible and OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Due to OE being routed through a register, the active state of the outputs cannot be determined prior to the arrival of the first clock pulse. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

The SN74ALVCH32501KR from Texas Instruments is a 36-bit universal bus transceiver in a 114-BGA MICROSTAR (16x5.5) package.

The SN74GTLPH32916KR from Texas Instruments is a 34-bit universal bus transceiver Integrated Circuit in a 114-BGA MicroStar (16x5.5) package.

The SN74ALVC16834GQLR from Texas Instruments is an 18-bit universal bus driver in a 56-BGA Microstar Junior (7x4.5) package.

The SN74ALVCHR16269AVR from Texas Instruments is a registered bus exchanger Integrated Circuit with a 12 to 24-bit configuration, in a 56-TVSOP package.

The SN74ALVC16334DGVR from Texas Instruments is a 16-bit universal bus driver in a 48-TVSOP package.

The SN74ALVCH16269KR from Texas Instruments is a registered bus exchanger with a 12 to 24-bit configuration in a 56-BGA Microstar Junior (7x4.5) package.

The SN74ALVC16334DGGR from Texas Instruments is a 16-bit universal bus driver Integrated Circuit in a 48-TSSOP package.

SN74ALVCHR162601DL from Texas Instruments is a Integrated Circuit 18-bit universal bus transceiver with 3-state outputs - General-purpose transceivers

SN74ABT16500BDL from Texas Instruments is a Integrated Circuit 18-bit universal bus transceivers with 3-state outputs - General-purpose transceivers. These 18-bit universal bus transceivers combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the high-to-low transition of CLKAB. OEAB is active-high. When OEAB is high, the outputs are active. When OEAB is low, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are complementary (OEAB is active high and OEBA is active low). When V CC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE should be tied to V CC through a pullup resistor and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver. The SN54ABT16500B is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT16500B is characterized for operation from -40°C to 85°C.

The SN74ALVCH16501KR from Texas Instruments is an 18-bit universal bus transceiver Integrated Circuit in a 56-BGA Microstar Junior (7x4.5) package.

The 74ALVCH16334DGGRE4 from Texas Instruments is a 16-bit universal bus driver Integrated Circuit in a 48-TSSOP package.

The 74GTLPH16912VRE4 from Texas Instruments is an 18-bit universal bus transceiver in a 56-TVSOP package.

The CD74HC299E from Texas Instruments is a universal 8-bit shift register Integrated Circuit in a 20-PDIP package.

The SN74VMEH22501DGG from Texas Instruments is an 8-bit universal bus function logic Integrated Circuit.

The SNJ54ABTH18502AHV from Texas Instruments is a scan test device Integrated Circuit from the universal bus functions subfamily.

The SNJ54LVTH18502AHV from Texas Instruments is a 3.3 V ABT scan test Integrated Circuit.