Universal Bus Functions

The 74ALVCH32501ZKFR from Texas Instruments is a 36-bit universal bus transceiver in a 114-BGA MicroStar package (16x5.5).

The SN74ALVCH16334DGVR from Texas Instruments is a 16-bit universal bus driver Integrated Circuit in a 48-TVSOP package.

SN74ALVCH162836GR from Texas Instruments is a Integrated Circuit 20-Bit Universal Bus Driver With 3-State Outputs - General-purpose transceivers. This 20-bit universal bus driver is designed for 1.65-V to 3.6-V V CC operation. Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode when the latch-enable (LE) input is low. When LE is high, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is high, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE is high, the outputs are in the high-impedance state. The output port includes equivalent 26- series resistors to reduce overshoot and undershoot. To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN74ALVCH162836 is characterized for operation from -40°C to 85°C.

The SN74ALVC162334DGGR from Texas Instruments is a universal bus driver Integrated Circuit with 16 bits, in a 48-TSSOP package.

The SN74ALVCH162334GR from Texas Instruments is a 16-bit universal bus driver Integrated Circuit in a 48-TSSOP package.

The SN74ALVC162835DGVR from Texas Instruments is an 18-bit universal bus driver Integrated Circuit in a 56-TVSOP package.

SN74GTLPH16912GR from Texas Instruments is a Integrated Circuit 18-Bit LVTTL-to-GTLP Universal Bus Transceiver - Voltage translators. The SN74GTLPH16912 is a medium-drive, 18-bit UBT™ transceiver that provides LVTTL-to-GTLP and GTLP-to-LVTTL signal-level translation. It allows for transparent, latched, clocked, and clock-enabled modes of data transfer. The device provides a high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal levels. High-speed (about three times faster than standard TTL or LVTTL) backplane operation is a direct result of GTLP's reduced output swing (<1 V), reduced input threshold levels, improved differential input, OEC™ circuitry, and TI-OPC™ circuitry. Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have been designed and tested using several backplane models. The medium drive allows incident-wave switching in heavily loaded backplanes with equivalent load impedance down to 19. GTLP is the Texas Instruments (TI™) derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The ac specification of the SN74GTLPH16912 is given only at the preferred higher noise-margin GTLP, but the user has the flexibility of using this device at either GTL (V TT = 1.2 V and V REF = 0.8 V) or GTLP (V TT = 1.5 V and V REF = 1 V) signal levels. Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels, but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. V REF is the B-port differential input reference voltage. This device is fully specified for live-insertion applications using I off, power-up 3-state, and BIAS V CC. The I off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The BIAS V CC circuitry precharges and preconditions the B-port input/output connections, preventing disturbance of active data on the backplane during card insertion or removal, and permits true live-insertion capability. This GTLP device features TI-OPC circuitry, which actively limits overshoot caused by improperly terminated backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves signal integrity, which allows adequate noise margin to be maintained at higher frequencies. Active bus-hold circuitry holds unused or undriven LVTTL data inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. When V CC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, the output-enable (OE) input should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74ALVC16834ZQLR from Texas Instruments is an 18-bit universal bus driver Integrated Circuit in a 56-BGA Microstar Junior (7x4.5) package.

SN74ALVCH162268DL from Texas Instruments is a Integrated Circuit 12-bit to 24-bit registered bus exchanger with 3-state outputs - General-purpose transceivers. This 12-bit to 24-bit registered bus exchanger is designed for 1.65-V to 3.6-V V CC operation. The SN74ALVCH162268 is used for applications in which data must be transferred from a narrow high-speed bus to a wide, lower-frequency bus. The device provides synchronous data exchange between the two ports. Data is stored in the internal registers on the low-to-high transition of the clock (CLK) input when the appropriate clock-enable (CLKEN) inputs are low. The select (SEL) line is synchronous with CLK and selects 1B or 2B input data for the A outputs. For data transfer in the A-to-B direction, a two-stage pipeline is provided in the A-to-1B path, with a single storage register in the A-to-2B path. Proper control of these inputs allows two sequential 12-bit words to be presented synchronously as a 24-bit word on the B port. Data flow is controlled by the active-low output enables (OEA, OEB). These control terminals are registered, so bus direction changes are synchronous with CLK. The B outputs, which are designed to sink up to 12 mA, include equivalent 26- resistors to reduce overshoot and undershoot. To ensure the high-impedance state during power up or power down, a clock pulse should be applied as soon as possible and OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Due to OE being routed through a register, the active state of the outputs cannot be determined prior to the arrival of the first clock pulse. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

The SN74GTLPH16916VR from Texas Instruments is a 17-bit universal bus transceiver in a 56-TVSOP package.

The SCAN16512ASM/NOPB from Texas Instruments is a 16-bit universal bus transceiver in a 64-NFBGA (8x8) package.

The SN74ALVCH16334DGGR from Texas Instruments is a 16-bit universal bus driver Integrated Circuit in a 48-TSSOP package.

SN74ALVCF162835GR from Texas Instruments is a Integrated Circuit 3.3-V CMOS 18-Bit Universal Bus Driver with 3-State Outputs - General-purpose transceivers. This 18-bit universal bus driver is designed for 2.3-V to 3.6-V V CC operation. Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode when the latch-enable (LE) input is high. When LE is low, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE is high, the outputs are in the high-impedance state. The SN74ALVCF162835 has series damping resistors in the device output structure that reduce switching noise in 128-MB and 256-MB SDRAM modules. Designed with a drive capability of ±18 mA, this device is a midway drive between the SN74ALVC162835 (±12 mA) and SN74ALVC16835 (±24 mA). The SN74ALVCF162835 is a faster version of the SN74ALVC162835. It is suitable for PC133 applications and, particularly, SDRAM modules clocked at 133 MHz. To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SCAN162512ASM/NOPB from Texas Instruments is a 16-bit universal bus transceiver Integrated Circuit in a 64-NFBGA (8x8) package.

The SN74GTL16923DGGR from Texas Instruments is an 18-bit universal bus transceiver Integrated Circuit in a 64-TSSOP package.

The SN74ALVC16835ZQLR from Texas Instruments is an 18-bit universal bus driver in a 56-BGA Microstar Junior (7x4.5) package.

SN74ALVC16835DL from Texas Instruments is a Integrated Circuit 18-Bit Universal Bus Driver With 3-State Outputs - General-purpose transceivers. This 18-bit universal bus driver is designed for 1.65-V to 3.6-V V CC operation. Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode when the latch-enable (LE) input is high. The A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE is high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

SN74ALVCH16601DGGR from Texas Instruments is a Integrated Circuit 18-bit universal bus transceiver with 3-state outputs - General-purpose transceivers. This 18-bit universal bus transceiver is designed for 1.65-V to 3.6-V V CC operation. The SN74ALVCH16601 combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB and CLKENBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. Output enable OEAB is active low. When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, CLKBA, and CLKENBA. To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN74ALVCH16601 is characterized for operation from -40°C to 85°C.

The SN74GTLPH32916ZKFR from Texas Instruments is a 34-bit universal bus transceiver in a 114-BGA MICROSTAR (16x5.5) package.

The SCAN16512SM from Texas Instruments is a 16-bit universal bus transceiver in a 64-NFBGA (8x8) package (also given as 64-FBGA).

The SN74AVC16834DGVR from Texas Instruments is an 18-bit universal bus driver Integrated Circuit in a 56-TVSOP package.