Universal Bus Functions

The 74SSTL16837ADGGRE4 from Texas Instruments is a 20-bit universal bus driver Integrated Circuit supplied in a 64-TSSOP package.

SN74ALVCF162834DL from Texas Instruments is a Integrated Circuit 3.3-V CMOS 18-Bit Universal Bus Driver with 3-State Outputs - General-purpose transceivers. This 18-bit universal bus driver is designed for 2.3-V to 3.6-V V CC operation. Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode when the latch-enable (LE) input is low. When LE is high, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is high, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE is high, the outputs are in the high-impedance state. The ALVCF162834 has series damping resistors in the device output structure that reduce switching noise in 128-MB and 256-MB SDRAM modules. Designed with a drive capability of ±18 mA, this device is a midway drive between the ALVC162834 (±12 mA) and ALVC16834 (±24 mA). The SN74ALVCF162834 is a faster version of the SN74ALVC162834. It is suitable for PC133 applications, particularly for SDRAM modules clocked at 133 MHz. To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

SN74ALVCH16835DGGR from Texas Instruments is a Integrated Circuit 18-Bit Universal Bus Driver With 3-State Outputs - General-purpose transceivers. This 18-bit universal bus driver is designed for 1.65-V to 3.6-V V CC operation. Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode when the latch-enable (LE) input is high. The A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE is high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

The SN74ALVC162836DGVR from Texas Instruments is a universal bus driver Integrated Circuit with 20 bits, in a 56-TVSOP package.

SN74ALVTH16601DLR from Texas Instruments is a Integrated Circuit 2.5-V/3.3-V 18-bit universal bus transceiver with 3-state outputs - General-purpose transceivers. The 'ALVTH16601 devices are 18-bit universal bus transceivers designed for 2.5-V or 3.3-V V CC operation, but with the capability to provide a TTL interface to a 5-V system environment. The devices combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB and CLKENBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. Output enable OEAB is active low. When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, CLKBA, and CLKENBA. This device is fully specified for hot-insertion applications using I off and power-up 3-state. The I off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. When V CC is between 0 and 1.2 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2 V, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN54ALVTH16601 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALVTH16601 is characterized for operation from -40°C to 85°C.

The SN74ABTH32501PZ from Texas Instruments is a universal bus transceiver Integrated Circuit with 36 bits, in a 100-LQFP package.

The NTE74HC299 from NTE Electronics, Inc is a high-speed CMOS universal shift register Integrated Circuit with 8 bits, in a 20-DIP package.

The CVMEH22501AIDGGREP from Texas Instruments is a universal bus transceiver with an 8-bit and dual 1-bit configuration, in a 48-TSSOP package.

SN74ALVCH16270DLR from Texas Instruments is a Integrated Circuit 12-bit to 24-bit registered bus exchanger with 3-state outputs - General-purpose transceivers. This 12-bit to 24-bit registered bus exchanger is designed for 1.65-V to 3.6-V V CC operation. The SN74ALVCH16270 is used in applications in which data must be transferred from a narrow high-speed bus to a wide lower-frequency bus. The device provides synchronous data exchange between the two ports. Data is stored in the internal registers on the low-to-high transition of the clock (CLK) input when the appropriate CLKEN inputs are low. The select (SEL) line selects 1B or 2B data for the A outputs. For data transfer in the A-to-B direction, a two-stage pipeline is provided in the A-to-1B path, with a single storage register in the A-to-2B path. Proper control of the CLKENA inputs allows two sequential 12-bit words to be presented synchronously as a 24-bit word on the B port. Data flow is controlled by the active-low output enables (OEA, OEB). The control terminals are registered to synchronize the bus-direction changes with CLK. To ensure the high-impedance state during power up or power down, a clock pulse should be applied as soon as possible, and OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Due to OE being routed through a register, the active state of the outputs cannot be determined prior to the arrival of the first clock pulse. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN74ALVCH16270 is characterized for operation from -40°C to 85°C.

SN74ALVCH16270DL from Texas Instruments is a Integrated Circuit 12-bit to 24-bit registered bus exchanger with 3-state outputs - General-purpose transceivers. This 12-bit to 24-bit registered bus exchanger is designed for 1.65-V to 3.6-V V CC operation. The SN74ALVCH16270 is used in applications in which data must be transferred from a narrow high-speed bus to a wide lower-frequency bus. The device provides synchronous data exchange between the two ports. Data is stored in the internal registers on the low-to-high transition of the clock (CLK) input when the appropriate CLKEN inputs are low. The select (SEL) line selects 1B or 2B data for the A outputs. For data transfer in the A-to-B direction, a two-stage pipeline is provided in the A-to-1B path, with a single storage register in the A-to-2B path. Proper control of the CLKENA inputs allows two sequential 12-bit words to be presented synchronously as a 24-bit word on the B port. Data flow is controlled by the active-low output enables (OEA, OEB). The control terminals are registered to synchronize the bus-direction changes with CLK. To ensure the high-impedance state during power up or power down, a clock pulse should be applied as soon as possible, and OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Due to OE being routed through a register, the active state of the outputs cannot be determined prior to the arrival of the first clock pulse. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN74ALVCH16270 is characterized for operation from -40°C to 85°C.

SN74ALVCHR16601DL from Texas Instruments is a Integrated Circuit 18-Bit Universal Bus Transceiver With 3-State Outputs - General-purpose transceivers. This 18-bit universal bus transceiver is designed for 1.65-V to 3.6-V V CC operation. The SN74ALVCHR16601 combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, clocked, and clock-enabled modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB and CLKENBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, CLKBA, and CLKENBA. The outputs include equivalent 26- series resistors to reduce overshoot and undershoot. To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

The SN74ALVCH162835VR from Texas Instruments is an 18-bit universal bus driver Integrated Circuit in a 56-TVSOP package.

The SN74ALVC16835DGVR from Texas Instruments is an 18-bit universal bus driver Integrated Circuit, in a 56-TVSOP package.

SN74ALVTH16601DL from Texas Instruments is a Integrated Circuit 2.5-V/3.3-V 18-bit universal bus transceiver with 3-state outputs - General-purpose transceivers. The 'ALVTH16601 devices are 18-bit universal bus transceivers designed for 2.5-V or 3.3-V V CC operation, but with the capability to provide a TTL interface to a 5-V system environment. The devices combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB and CLKENBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. Output enable OEAB is active low. When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, CLKBA, and CLKENBA. This device is fully specified for hot-insertion applications using I off and power-up 3-state. The I off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. When V CC is between 0 and 1.2 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2 V, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN54ALVTH16601 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALVTH16601 is characterized for operation from -40°C to 85°C.

The SN74ALVCF162835VR from Texas Instruments is an 18-bit universal bus driver Integrated Circuit, in a 56-TVSOP package.

SN74ALVTH16601VR from Texas Instruments is a Integrated Circuit 2.5-V/3.3-V 18-bit universal bus transceiver with 3-state outputs - General-purpose transceivers. The 'ALVTH16601 devices are 18-bit universal bus transceivers designed for 2.5-V or 3.3-V V CC operation, but with the capability to provide a TTL interface to a 5-V system environment. The devices combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB and CLKENBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. Output enable OEAB is active low. When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, CLKBA, and CLKENBA. This device is fully specified for hot-insertion applications using I off and power-up 3-state. The I off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. When V CC is between 0 and 1.2 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2 V, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN54ALVTH16601 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALVTH16601 is characterized for operation from -40°C to 85°C.

The 74FCT162501ATPACT from Cypress Semiconductor Corp is a universal bus transceiver Integrated Circuit with 18-bit width, in a 56-TSSOP package.

The 74FCT162500ATPVCT from Cypress Semiconductor Corp is a universal bus transceiver Integrated Circuit with 18-bit width, in a 56-SSOP package.

The 74FCT162501ETPACT from Cypress Semiconductor Corp is an 18-bit universal bus transceiver from the FCT series, in a 56-TSSOP package.

The 74FCT162501ATPVCT from Cypress Semiconductor Corp is an 18-bit universal bus function Integrated Circuit (CY74FCT162501T).

The SN74ABTH18504APMR from Texas Instruments is a 20-bit scan test universal bus transceiver in a 64-LQFP package measuring 10x10.

The SN74ALVCH162334VR from Texas Instruments is a 16-bit universal bus driver Integrated Circuit, in a 48-TVSOP package.