Search results for “universal bus functions”

SN74ALVCF162835GR from Texas Instruments is a Integrated Circuit 3.3-V CMOS 18-Bit Universal Bus Driver with 3-State Outputs - General-purpose transceivers. This 18-bit universal bus driver is designed for 2.3-V to 3.6-V V CC operation. Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode when the latch-enable (LE) input is high. When LE is low, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE is high, the outputs are in the high-impedance state. The SN74ALVCF162835 has series damping resistors in the device output structure that reduce switching noise in 128-MB and 256-MB SDRAM modules. Designed with a drive capability of ±18 mA, this device is a midway drive between the SN74ALVC162835 (±12 mA) and SN74ALVC16835 (±24 mA). The SN74ALVCF162835 is a faster version of the SN74ALVC162835. It is suitable for PC133 applications and, particularly, SDRAM modules clocked at 133 MHz. To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

SN74ALVCF162834DL from Texas Instruments is a Integrated Circuit 3.3-V CMOS 18-Bit Universal Bus Driver with 3-State Outputs - General-purpose transceivers. This 18-bit universal bus driver is designed for 2.3-V to 3.6-V V CC operation. Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode when the latch-enable (LE) input is low. When LE is high, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is high, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE is high, the outputs are in the high-impedance state. The ALVCF162834 has series damping resistors in the device output structure that reduce switching noise in 128-MB and 256-MB SDRAM modules. Designed with a drive capability of ±18 mA, this device is a midway drive between the ALVC162834 (±12 mA) and ALVC16834 (±24 mA). The SN74ALVCF162834 is a faster version of the SN74ALVC162834. It is suitable for PC133 applications, particularly for SDRAM modules clocked at 133 MHz. To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

SN74ALVCH16334DL from Texas Instruments is a Integrated Circuit 16-Bit Universal Bus Driver With 3-State Outputs - General-purpose transceivers. This 16-bit universal bus driver is designed for 1.65-V to 3.6-V V CC operation. Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode when the latch-enable (LE) input is low. When LE is high, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is high, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE is high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN74ALVCH16334 is characterized for operation from -40°C to 85°C.

SN74ALVC162835DGGR from Texas Instruments is a Integrated Circuit 18-Bit Universal Bus Driver With 3-State Outputs - General-purpose transceivers. This 18-bit universal bus driver is designed for 1.65-V to 3.6-V V CC operation. Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode when the latch-enable (LE) input is high. When LE is low, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE is high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The output port includes equivalent 26- series resistors to reduce overshoot and undershoot.

SN74ALVC162836DL from Texas Instruments is a Integrated Circuit 20-Bit Universal Bus Driver With 3-State Outputs - General-purpose transceivers. This 20-bit universal bus driver is designed for 1.65-V to 3.6-V V CC operation. Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode when the latch-enable (LE) input is low. When LE is high, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is high, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE is high, the outputs are in the high-impedance state. The output port includes equivalent 26- series resistors to reduce overshoot and undershoot. To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

74LVTH16501MTDX from onsemi is a TXRX 18BIT UNIV BUS 3ST 56TSSOP

74AVC16834ADGV,112 from NXP USA Inc. is a IC UNIV BUS DVR 18BIT 56TVSOP

SN74ALVC162334DLR from Texas Instruments is a Integrated Circuit 16-Bit Universal Bus Driver With 3-State Outputs - General-purpose transceivers. This 16-bit universal bus driver is designed for 1.65-V to 3.6-V V CC operation. Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode when the latch-enable (LE) input is low. When LE is high, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is high, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE is high, the outputs are in the high-impedance state. The outputs, which are designed to sink up to 12 mA, include equivalent 26- resistors to reduce overshoot and undershoot. To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

74VCX16500MTDX from onsemi is a TXRX 18BIT UNIV BUS LV 56TSSOP

SN74ALVCH162334DL from Texas Instruments is a Integrated Circuit 16-Bit Universal Bus Driver With 3-State Outputs - General-purpose transceivers. This 16-bit universal bus driver is designed for 1.65-V to 3.6-V V CC operation. Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode when the latch-enable (LE) input is low. When LE is high, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is high, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE is high, the outputs are in the high-impedance state. The output port includes equivalent 26- series resistors to reduce overshoot and undershoot. To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN74ALVCH162334 is characterized for operation from -40°C to 85°C.

SN74ABT16500BDL from Texas Instruments is a Integrated Circuit 18-bit universal bus transceivers with 3-state outputs - General-purpose transceivers. These 18-bit universal bus transceivers combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the high-to-low transition of CLKAB. OEAB is active-high. When OEAB is high, the outputs are active. When OEAB is low, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are complementary (OEAB is active high and OEBA is active low). When V CC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE should be tied to V CC through a pullup resistor and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver. The SN54ABT16500B is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT16500B is characterized for operation from -40°C to 85°C.

SN74ALVCH16524DL from Texas Instruments is a Integrated Circuit 18-Bit Registered Bus Transceiver With 3-State Outputs - General-purpose transceivers. This 18-bit universal bus transceiver is designed for 1.65-V to 3.6-V V CC operation. Data flow in each direction is controlled by output-enable (OEAB and OEBA) and clock-enable (CLKENBA) inputs. For the A-to-B data flow, the data flows through a single buffer. The B-to-A data can flow through a four-stage pipeline register path, or through a single register path, depending on the state of the select (SEL) input. Data is stored in the internal registers on the low-to-high transition of the clock (CLK) input, provided that the appropriate CLKENBA input is low. The B-to-A data transfer is synchronized with CLK. To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

74ALVCH162601DGG512 from NXP USA Inc. is a REGISTERED BUS TRANSCEIVER

74ALVC16601MTDX from onsemi is a TXRX 18BIT UNIV BUS 56TSSOP